1. Field of the Invention
This invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having input/output (I/O) cells and/or power source cells.
2. Description of the Related Art
In a semiconductor integrated circuit, I/O cells are often arranged in multistage in order to cope with the multiplication of pins. The arrangement intervals for I/O cells in a multistage configuration are such that both outer I/O cells and inner I/O cells are arranged at predetermined intervals.
FIGS. 7A and 7B show a semiconductor integrated circuit having a configuration in which I/O cells are arranged in multistage according to a first prior art.
FIG. 7A shows a configuration of a semiconductor integrated circuit (semiconductor chip) 700. The semiconductor integrated circuit 700 has a first group of cells 701, a second group of cells 702, and a third group of cells 703 along the circumferential frame region thereof, and effective circuit cells in an internal region 704. Respective plural I/O cells of the first to the third group of cells 701 to 703 are arranged annularly along a direction of the outer periphery. The first group of cells 701, the second group of cells 702, and the third group of cells 703 are, respectively, the outermost group of cells, the second outermost group of cells, and the third outermost group of cells, in the semiconductor integrated circuit 700.
FIG. 7B is an enlarged view of a region 705 which is a part of the semiconductor integrated circuit shown in FIG. 7A. The region 705 includes the first group of cells 701, the second group of cells 702, and the third group of cells 703. In each group of cells 701 to 703, a plurality of I/O cells 711 are disposed. In this configuration, the size and the arrangement interval of the I/O cells 711 are constant. The I/O cells 711 are hard-wired with the cells within the internal region 704 (FIG. 7A). Hence, the more innerly a group of cells is located, the more difficult is the wiring between the I/O cells 711 in the wire region 712 therein. For example, in the case of a wire 713, wiring is impractical because there is no wiring channel remaining. Even when wiring is coaxed, a long detour is required so that the wire has to be longer in length. Further, as is the case with the wire region 712, the more innerly a group of cells is located, the more congested the wiring is, becoming more susceptible to crosstalk. In the worst case thereof, a required performance cannot be achieved.
FIGS. 8A and 8B show a semiconductor integrated circuit having a configuration in which I/O cells are arranged in multistage according to a second prior art. FIG. 8A shows the configuration of a semiconductor integrated circuit 700 as in FIG. 7A. FIG. 8B is an enlarged view of a region 805 which is a part of the semiconductor integrated circuit shown in FIG. 8A. The region 805 includes a first group of cells 701, a second group of cells 702, and a third group of cells 703. In the first group of cells 701, a plurality of I/O cells 811 are arranged. In the second group of cells 702, a plurality of I/O cells 812 each of them being smaller than the I/O cell 811 in size are arranged. In the third group of cells 703, I/O cells 813 each of them being smaller than the I/O cell 812 in size are arranged. The number of cells for the groups of cells 701 to 703 is identical.
In the above configuration, the more innerly a group of cells is located, the smaller is the size of I/O cells thereof. Accordingly, as seen in a wiring region 814, the wiring region is wide enough so that there is no wiring difficulty. However, since the more innerly located group of cells includes the smaller I/O cells, a large variety of types of I/O cells having the same function have to be prepared, costing an enormous number of man-hours for the development. Further, there is a problem that in general, the electrostatic withstand voltage of the smaller I/O cells are lower where the structure of the transistors are uniform.
Still another prior art is also published in the following patent document 1.
[Patent Document 1]
Japanese Patent Laid-open No. Hei 11-150204